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ltm8031 1 8031fb typical a pplica t ion descrip t ion ultralow noise emc 36v, 1a dc/dc module regulator the ltm ? 8031 is an electromagnetic compatible (emc) 36v, 1a dc/dc module ? buck converter designed to meet the radiated emissions requirements of en55022. conducted emission requirements can be met by adding standard flter components. included in the package are the switching controller, power switches, inductor, flters and all support components. operating over an input voltage range of 3.6v to 36v, the ltm8031 supports an output voltage range of 0.8v to 10v, and a switching frequency range of 200khz to 2.4mhz, each set by a single resistor. only the bulk input and output flter capacitors are needed to fnish the design. the low profle package (2.82mm) enables utilization of unused space on the bottom of pc boards for high density point of load regulation. the ltm8031 is packaged in a thermally enhanced, compact (9mm 15mm) and low profle (2.82mm) overmolded land grid array (lga) package suitable for automated assembly by standard surface mount equipment. the ltm8031 is rohs compliant. ultralow noise 5v/1a dc/dc module regulator fea t ures a pplica t ions n complete step-down switch mode power supply n wide input voltage range: 3.6v to 36v n 1a output current n 0.8v to 10v output voltage n switching frequency from 200khz to 2.4mhz n en55022 class b compliant with margin n current mode control n (e4) rohs compliant package with gold pad finish n programmable soft-start n pin compatible with the ltm8032 n low profle (9mm 15mm 2.82mm) surface mount lga package n automotive battery regulation n power for portable products n distributed supply regulation n industrial supplies n wall transformer regulation ltm8031 emi performance l , lt, ltc, ltm, module, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. rt share 47.5k 44.2k *running voltage range. see applications for start-up details v in fin 1f 10f v out 5v 1a run/ss v in * 7vdc to 36vdc pgood bias ltm8031 aux out sync gnd 8031 ta01a adj frequency (mhz) 0 emissions level (dbv/m) 50 70 800 8031 ta01b 30 en55022 class b limit 10 40 60 80 20 0 ?10 200100 400300 600 700 900 500 1000 v in = 36v
ltm8031 2 8031fb v in , fin, run/ss voltage .......................................... 40v adj, rt, share v oltage ............................................. 5v v out , aux ................................................................. 10v current from aux ................................................ 100ma pgood, sync .......................................................... 30v bias .......................................................................... 25v v in + bias ................................................................. 56v maximum junction temperature (note 2) ............. 125c solder temperature (note 3) ................................. 245c (note 1) gnd 1 a b c bank 1 bank 2 bank 3 d e f g h j k l 2 3 4 top view lga package 71-lead (9mm 15mm 2.82mm) 5 6 7 v out v in rt share adj pgood sync run/ss fin bias aux t jmax = 125c, ja = 20.7c/w, jc(bottom) = 8.4c/w, jc(top) = 25.6c/w, jboard = 13.8c/w values determined per jesd 51-9 weight = 1.2g p in c on f igura t ion a bsolu t e maxi m u m r a t ings lead free finish tray part marking* package description temperature range ltm8031ev#pbf ltm8031ev#pbf ltm8031v 71-lead (9mm 15mm 2.82mm) lga C40c to 125c ltm8031iv#pbf ltm8031iv#pbf ltm8031v 71-lead (9mm 15mm 2.82mm) lga C40c to 125c ltm8031mpv#pbf ltm8031mpv#pbf ltm8031v 71-lead (9mm 15mm 2.82mm) lga C55c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ or d er in f or m a t ion
ltm8031 3 8031fb e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm8031e is guaranteed to meet performance specifcations from 0c to 125c internal. specifcations over the C40c to 125c internal temperature range are assured by design, characterization and correlation with statistical process controls. the ltm8031i is guaranteed the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 10v, v run/ss = 10v, v bias = 3v, unless otherwise specifed. symbol parameter conditions min typ max units v in input dc voltage l 3.6 36 v v out output dc voltage 0.2a < i out 1a, r adj open 0.2a < i out 1a, r adj = 21.6k 0.8 10 v v i out continuous output dc current v in = 24v 1 a i q(vin) v in quiescent current v run/ss = 0.2v v bias = 3v, not switching v bias = 0v, not switching l 0.6 25 88 60 120 a a a i q(bias) bias quiescent current v run/ss = 0.2v v bias = 3v, not switching v bias = 0v, not switching l 0.03 60 1 120 5 a a a ?v out v out line regulation 10v v in 36v, i out = 1a, v out = 3.3v 0.1 % load regulation v in = 24v, 0.2a i out 1a, v out = 3.3v 0.3 % v out(ac_rms) output ripple (rms) v in = 24v, i out = 1a, v out = 3.3v 6 mv f sw switching frequency r t = 113k 325 khz v adj voltage at adj pin l 765 790 815 mv v bias(min) minimum bias voltage for proper operation 1.9 2.8 v i adj current out of adj pin v run/ss = 0v, v adj = 0v, v out = 1v 4 a i run/ss run/ss pin current v run/ss = 2.5v 5 10 a v ih(run/ss) run/ss input high voltage 2.5 v v il(run/ss) run/ss input low voltage 0.2 v v pg(th) adj voltage threshold for pgood to switch 730 mv i pgo pgood leakage v pg = 30v 0.1 1 a i pgsink pgood sink current v pg = 0.4v 200 800 a v syncil sync input low threshold f sync = 550khz 0.5 v v syncih sync input high threshold f sync = 550khz 0.7 v i sync(bias) sync pin bias current v sync = 0v, v bias = 0v 0.1 a v in(ripple) 550khz narrowband conducted emission 1mhz narrowband conducted emission 3mhz narrowband conducted emission v in = 24v, v out = 3.3v, i out = 1a, f sw = 550khz, 5h lisn 83 63 51 dbv dbv dbv to meet specifcations over the full C40c to 125c internal operating temperature range. the ltm8031mp is guaranteed to meet specifcations over the full C55c to 125c internal operating temperature range. note that the maximum internal temperature is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: see linear technology application note 100.
ltm8031 4 8031fb typical p er f or m ance c harac t eris t ics input current vs output current, 3.3v out input current vs output current, 5v out input current vs output current, 8v out minimum v in vs output current 2.5v v out 3.3v out effciency 5v out effciency 8v out effciency t a = 25c, unless otherwise noted. minimum v in vs output current 3.3v v out minimum v in vs output current 5v v out output current (ma) 0 40 efficiency (%) 50 60 70 80 90 100 200 400 600 800 8031 g01 1000 5v in 12v in 24v in 36v in output current (ma) 0 40 efficiency (%) 50 60 70 80 90 100 200 400 600 800 8031 g02 1000 12v in 24v in 36v in output current (ma) 0 40 efficiency (%) 50 60 70 80 90 100 200 400 600 800 8031 g03 1000 12v in 24v in 36v in output current (ma) 0 input current (ma) 300 400 500 600 1000 8031 g04 200 100 0 200 400 800 600 700 800 5v in 12v in 24v in 36v in output current (ma) 0 input current (ma) 300 400 500 800 8031 g05 200 100 250 350 450 150 50 0 200 400 600 1000 12v in 24v in 36v in output current (ma) 0 input current (ma) 300 400 500 600 1000 8031 g06 200 100 0 200 400 800 600 700 800 12v in 24v in 36v in output current (ma) 0 v in (v) 4.0 4.2 4.4 600 1000 8031 g07 3.8 3.6 3.4 200 400 800 4.6 4.8 5.0 run/ss = v in or toggled running output current (ma) 0 v in (v) 5.1 5.6 6.1 800 8031 g08 4.6 4.1 3.6 200 400 600 1000 run/ss toggled run/ss = v in running output current (ma) 0 v in (v) 5.1 5.6 6.1 600 1000 8031 g09 4.6 4.1 3.6 200 400 800 6.6 7.1 7.6 run/ss = v in running or run/ss toggled
ltm8031 5 8031fb typical p er f or m ance c harac t eris t ics output current vs input voltage (output shorted) input current vs input voltage (output shorted) temperature rise vs load current, v out = 3.3v temperature rise vs load current, v out = 5v temperature rise vs load current, v out = 8v minimum v in vs output current 8v v out minimum input running voltage vs output voltage, i out = 1a bias current vs output current t a = 25c, unless otherwise noted. temperature rise vs load current, v out = 10v output current (ma) 0 v in (v) 7 8 9 600 1000 8031 g10 6 5 4 200 400 800 10 11 12 run/ss = v in running or run/ss toggled v out (v) 0 v in (v) 6 8 10 6 10 8031 g11 4 2 0 2 4 8 12 14 16 output current (ma) 0 25 30 35 800 8031 g12 20 15 200 400 600 1000 10 5 0 bias current (ma) 8v out 5v out 3.3v out v in (v) 0 output current (a) 2.55 2.60 2.65 32 8031 g13 2.50 2.45 2.35 8 16 24 4 36 12 20 28 2.40 2.75 2.70 v in (v) 0 0.8 1.0 1.4 30 8031 g14 0.6 0.4 10 20 40 0.2 0 1.2 input current (a) output current (ma) 0 0 temperature rise (c) 5 10 15 20 25 30 200 400 600 800 8031 g15 1000 36v in 24v in 12v in 5v in output current (ma) 1 0 temperature rise (c) 5 10 15 20 25 30 200 400 600 800 8031 g16 1000 36v in 24v in 12v in output current (ma) 1 0 temperature rise (c) 5 10 15 20 25 30 200 400 600 800 8031 g17 1000 36v in 24v in 12v in output current (ma) 1 0 temperature rise (c) 5 10 15 20 25 30 200 400 600 800 8031 g18 1000 36v in 24v in
ltm8031 6 8031fb typical p er f or m ance c harac t eris t ics radiated emissions radiated emissions t a = 25c, unless otherwise noted. p in func t ions v in (bank 3): the v in pin supplies current to the ltm8031s internal regulator and to the internal power switch. this pin must be locally bypassed with an external, low esr capacitor of at least 1f . fin (k3, l3): filtered input. this is the node after the input emi flter . use this only if there is a need to modify the behavior of the integrated emi flter or if v in rises or falls rapidly; otherwise, leave these pins unconnected. see the applications information section for more details. gnd (bank 2): tie these gnd pins to a local ground plane below the ltm8031 and the circuit components. return the feedback divider (r adj ) to this net. v out (bank 1): power output pins. apply the output flter capacitor and the output load between these pins and gnd pins. aux (pin h5): low current voltage source for bias. in many designs, the bias pin is simply connected to v out . the aux pin is internally connected to v out and is placed adjacent to the bias pin to ease printed circuit board rout - ing. although this pin is internally connected to v out , do not connect this pin to the load. if this pin is not tied to bias, leave it foating. bias (pin h4): the bias pin connects to the internal power bus. connect to a power source greater than 2.8v. if the output is greater than 2.8v, connect this pin to aux. if the output voltage is less, connect this to a voltage source between 2.8v and 25v. also, make sure that bias + v in is less than 56v. run/ss (pin l5): pull run/ss pin to less than 0.2v to shut down the ltm8031. tie to 2.5v or more for normal operation. if the shutdown feature is not used, tie this pin to the v in pin. run/ss also provides a soft-start function; see the applications information section. rt (pin g7): the rt pin is used to program the switching frequency of the ltm8031 by connecting a resistor from this pin to ground. the applications information section of the data sheet includes a table to determine the resistance value based on the desired switching frequency. minimize capacitance at this pin. share (pin h7): tie this to the share pin of another ltm8031 when paralleling the outputs. frequency (mhz) 0 emissions level (dbv/m) 50 70 90 v in = 36v v out = 10v at 1a 800 8031 g19 30 10 40 60 80 20 0 ?10 200100 400300 600 700 900 500 1000 en55022 class b limit frequency (mhz) 0 emissions level (dbv/m) 50 70 90 v in = 36v v out = 2.5v at 1a 800 8031 g20 30 10 40 60 80 20 0 ?10 200100 400300 600 700 900 500 1000 en55022 class b limit
ltm8031 7 8031fb p in func t ions sync (pin l6): this is the external clock synchronization input. ground this pin for low ripple burst mode ? operation at low output loads. tie to a stable voltage source greater than 0.7v to disable burst mode operation. do not leave this pin foating. tie to a clock source for synchroniza - tion. clock edges should have rise and fall times faster than 1s. see synchronization section in applications information. pgood (pin k7): the pgood pin is the open-collector output of an internal comparator. pgood remains low until the adj pin is within 10% of the fnal regulation voltage. the pgood output is valid when v in is above 3.6v and run/ss is high. if this function is not used, leave this pin foating. adj (pin j7): the ltm8031 regulates its adj pin to 0.79v. connect the adjust resistor from this pin to ground. the value of r adj is given by the equation: r adj = 196.71 v out ? 0.79 where r adj is in k. b lock diagra m current mode controller 249k 10f v out aux gnd 4.7h bias 22pf emi filter fin v in gnd share sync rt pgood adj 8031 bd run/ss
ltm8031 8 8031fb o pera t ion a pplica t ions i n f or m a t ion the ltm8031 is a standalone nonisolated step-down switching dc/dc power supply. it can deliver up to 1a of dc output current with only bulk external input and output capacitors. this module provides a precisely regulated output voltage programmable via one external resistor from 0.8vdc to 10vdc. the input voltage range is 3.6v to 36v. given that the ltm8031 is a step-down converter, make sure that the input voltage is high enough to support the desired output voltage and load current. a simplifed block diagram is given on the previous page. the ltm8031 is designed with an input emi flter and other features to make its radiated emissions compliant with several emc specifcations including en55022 class b. compliance with conducted emissions requirements may be obtained by adding a standard input flter. the l tm8031 contains a current mode controller, power switching element, power inductor, power schottky diode and a modest amount of input and output capacitance. the ltm8031 is a fxed frequency pwm regulator. the switch - ing frequency is set by simply connecting the appropriate resistor value from the rt pin to gnd. an internal regulator provides power to the control circuitry. the bias regulator can draw power from the v in pin, but if the bias pin is connected to an external voltage higher than 2.8v, bias power will be drawn from the external source (typically the regulated output voltage). this improves effciency. the run/ss pin is used to place the ltm8031 in shutdown, disconnecting the output and reducing the input current to less than 1a. to further optimize effciency, the ltm8031 automatically switches to burst mode operation in light load situations. between bursts, all circuitry associated with controlling the output switch is shut down reducing the input supply cur - rent to 50a in a typical application. the oscillator reduces the ltm8031s operating frequency when the voltage at the adj pin is low. this frequency foldback helps to control the output current during start-up and overload. the ltm8031 contains a power good comparator which trips when the adj pin is at 90% of its regulated value. the pgood output is an open-collector transistor that is off when the output is in regulation, allowing an external resistor to pull the pgood pin high. power good is valid when the ltm8031 is enabled and v in is above 3.6v. for most applications, the design process is straight forward, summarized as follows: 1. look at table 1 and fnd the row that has the desired input range and output voltage. 2 . apply the recommended c in , c out , r adj and r t values. 3. connect bias as indicated. as the integrated input emi flter may ring in response to an application of a step input voltage, a bulk capacitance, series resistance or some clamping mechanism may be required. see the hot-plugging safely section for details. while these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. capacitor selection considerations the c in and c out capacitor values in table 1 are the minimum recommended values for the associated oper - ating conditions. applying capacitor values below those indicated in table 1 is not recommended, and may result in undesirable operation. using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. again, it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental conditions. ceramic capacitors are small, robust and have very low esr. however, not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and applied voltage and give dependable service. other types, includ - ing y5v and z5u have very large temperature and voltage coeffcients of capacitance. in an application circuit they
ltm8031 9 8031fb a pplica t ions i n f or m a t ion table 1. recommended component values and confguration (see typical performance characteristics for load conditions) v in v out c in c out r adj bias f optimal r t(optimal) f max r t(min) 3.6v to 36v 0.82v 1f 0805 50v 2 100f 1206 6.3v 5.11m 2.8v, <25v 250khz 150k 250khz 150k 3.6v to 36v 1.20v 1f 0805 50v 100f//47f 1206 6.3v 475k 2.8v, <25v 300khz 124k 325khz 113k 3.6v to 36v 1.80v 1f 0805 50v 100f 1206 191k 2.8v, <25v 420khz 84.5k 450khz 78.7k 3.6v to 36v 2.00v 1f 0805 50v 100f 1206 162k 2.8v, <25v 450khz 78.7k 475khz 73.2k 3.6v to 36v 2.50v 1f 0805 50v 47f 0805 6.3v 115k 2.8v, <25v 550khz 61.9k 575khz 59.0k 4.75v to 36v 3.30v 1f 0805 50v 22f 1206 6.3v 78.7k aux 675khz 48.7k 725khz 44.2k 6.8v to 36v 5.00v 1f 0805 50v 10f 1206 6.3v 46.4k aux 975khz 29.4k 1000khz 28.0k 10.5v to 36v 8.00v 1f 0805 50v 4.7f 1206 10v 26.7k aux 1200khz 23.7k 1600khz 15.8k 13v to 36v 10.00v 1f 0805 50v 4.7f 0805 16v 21.0k aux 1250khz 22.6k 2050khz 10.5k 3.6v to 15v 0.82v 1f 0805 50v 2 100f 1206 6.3v 5.11m v in 500khz 69.8k 600khz 56.2k 3.6v to 15v 1.20v 1f 0805 50v 100f 1206 6.3v 475k v in 600khz 56.2k 750khz 42.2k 3.6v to 15v 1.80v 1f 0805 50v 100f 1206 191k v in 650khz 51.1k 1000khz 28.0k 3.6v to 15v 2.00v 1f 0805 50v 100f 1206 162k v in 650khz 51.1k 1100khz 26.7k 3.6v to 15v 2.50v 1f 0805 50v 47f 0805 6.3v 115k v in 700khz 47.5k 1350khz 20.5k 4.75v to 15v 3.30v 1f 0805 50v 22f 1206 6.3v 78.7k aux 950khz 32.4k 1650khz 15.0k 6.8v to 15v 5.00v 1f 0805 50v 10f 1206 6.3v 46.4k aux 1150khz 25.5k 2400khz 7.87k 10.5v to 15v 8.00v 1f 0805 50v 4.7f 1206 10v 26.7k aux 1200khz 23.7k 2400khz 7.87k 9v to 24v 0.82v 1f 0805 50v 2 100f 1206 6.3v 5.11m 2.8v, <25v 350khz 105k 375khz 93.1k 9v to 24v 1.20v 1f 0805 50v 100f//47f 1206 6.3v 475k 2.8v, <25v 450khz 78.7k 475khz 73.2k 9v to 24v 1.80v 1f 0805 50v 100f 1206 191k 2.8v, <25v 600khz 56.2k 650khz 51.1k 9v to 24v 2.00v 1f 0805 50v 100f 1206 162k 2.8v, <25v 650khz 51.1k 700khz 47.5k 9v to 24v 2.50v 1f 0805 50v 47f 0805 6.3v 115k 2.8v, <25v 700khz 47.5k 850khz 37.4k 9v to 24v 3.30v 1f 0805 50v 22f 1206 6.3v 78.7k aux 950khz 32.4k 1050khz 28.0k 9v to 24v 5.00v 1f 0805 50v 10f 1206 6.3v 46.4k aux 1150khz 25.5k 1550khz 16.5k 10.5v to 24v 8.00v 1f 0805 50v 4.7f 1206 10v 26.7k aux 1200khz 23.7k 2400khz 7.87k 13v to 24v 10.00v 1f 0805 50v 4.7f 0805 16v 21.0k aux 1250khz 22.6k 2400khz 7.87k note: an input bulk capacitor is required.
ltm8031 10 8031fb a pplica t ions i n f or m a t ion may have only a small fraction of their nominal capaci- tance resulting in much higher output voltage ripple than expected. ceramic capacitors are also piezoelectric. in burst mode operation, the ltm8031s switching frequency depends on the load current, and can excite a ceramic capacitor at audio frequencies, generating audible noise. since the ltm8031 operates at a lower current limit during burst mode operation, the noise is typically very quiet to a casual ear. if this audible noise is unacceptable, use a high performance electrolytic capacitor at the output. the input capacitor can be a parallel combination of a 1f ceramic capacitor and a low cost electrolytic capacitor. a fnal precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm8031. a ceramic input capacitor combined with trace or cable inductance forms a high q (under damped) tank circuit. if the ltm8031 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possi- bly exceeding the devices rating. this situation is easily avoided; see the hot-plugging safely section. electromagnetic compliance the ltm8031 is compliant with the radiated emissions requirements of en55022 class b. graphs of the ltm8031s emc performance are given in the typical performance characteristics section. further data, operating conditions and test setup are detailed in an emi test report available from linear technology. frequency selection the ltm8031 uses a constant frequency pwm architecture that can be programmed to switch from 200khz to 2.4mhz by using a resistor tied from the rt pin to ground. table 2 provides a list of r t resistor values and their resultant frequencies. operating frequency trade-offs it is recommended that the user apply the optimal r t value given in table 1 for the input and output operating condition. system level or other considerations, however, may necessitate another operating frequency. while the ltm8031 is fexible enough to accommodate a wide range of operating frequencies, a haphazardly chosen one may result in undesirable operation under certain operating or fault conditions. a frequency that is too high can reduce effciency, generate excessive heat or even damage the ltm8031 if the output is overloaded or short-circuited. a frequency that is too low can result in a fnal design that has too much output ripple or unnecessarily large output capacitor. the maximum frequency (and attendant r t value) at which the ltm8031 should be allowed to switch is given in table 1 in the f max column, while the recommended frequency (and r t value) for optimal effciency over the given input condition is given in the f optimal column. there are additional conditions that must be satisfed if the synchronization function is used. please refer to the synchronization section for details. table 2. switching frequency vs r t value switching frequency (mhz) r t value (k) 0.2 187 0.3 124 0.4 88.7 0.5 69.8 0.6 56.2 0.7 47.5 0.8 39.2 0.9 34 1.0 28.0 1.2 23.7 1.4 19.1 1.5 16.2 1.8 13.3 2 11.5 2.2 9.76 2.4 8.66
ltm8031 11 8031fb a pplica t ions i n f or m a t ion bias pin considerations the bias pin is used to provide drive power for the internal power switching stage and operate internal circuitry. for proper operation, it must be powered by at least 2.8v. if the output voltage is programmed to be 2.8v or higher, simply tie bias to aux. if v out is less than 2.8v, bias can be tied to v in or some other voltage source. in all cases, ensure that the maximum voltage at the bias pin is both less than 25v and the sum of v in and bias is less than 56v. if bias power is applied from a remote or noisy voltage source, it may be necessary to apply a decoupling capacitor locally to the ltm8031. load sharing two or more ltm8031s may be paralleled to produce higher currents. this may, however, alter the emi performance of the ltm8031s. to do this, tie the v in , adj, v out and share pins of all the paralleled ltm8031s together. to ensure that paralleled modules start up together, the run/ss pins may be tied together, as well. synchronize the ltm8031s to an external clock to eliminate beat frequencies, if required. if the run/ss pins are not tied together, make sure that the same valued soft-start capacitors are used for each module. an example of two ltm8031 modules confgured for load sharing is given in the typical applications sec - tion. for 2a applications also see the ltm8032, 2a emc dc/dc module regulator burst mode operation to enhance effciency at light loads, the ltm8031 auto - matically switches to burst mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the ltm8031 delivers single cycle bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. in addition, v in and bias quiescent currents are reduced to typically 25a and 60a respectively during the sleep time. as the load current decreases towards a no-load condition, the percentage of time that the ltm8031 operates in sleep mode increases and the average input current is greatly reduced, resulting in higher effciency. burst mode operation is enabled by tying sync to gnd. to disable burst mode operation, tie sync to a stable voltage above 0.7v. do not leave the sync pin foating. minimum input voltage the ltm8031 is a step-down converter, so a minimum amount of headroom is required to keep the output in regu - lation. in addition, the input voltage required to turn on is higher than that required to run, and depends upon whether the run/ss is used. as shown in the typical performance characteristics section, it takes only about 3.6v in for the ltm8031 to run a 3.3v output at light load. if run/ss is pulled up to v in , it takes 5.7v in to start. if the ltm8031 is enabled via the run/ss pin, the minimum voltage to start at light loads is lower, about 4.4v. similar curves for 2.5v out , 5v out and 8v out operation are also provided in the typical performance characteristics section. soft-start the run/ss pin can be used to soft-start the ltm8031, reducing the maximum input current during start-up. the run/ss pin is driven through an external rc network to create a voltage ramp at this pin. figure 1 shows the start- up and shutdown waveforms with the soft-start circuit. by choosing an appropriate rc time constant, the peak start-up current can be reduced to the current that is required to regulate the output, with no overshoot. choose the value of the resistor so that it can supply at least 20a when the run/ss pin reaches 2.5v.
ltm8031 12 8031fb synchronization the internal oscillator of the ltm8031 can be synchro - nized by applying an external 250khz to 2mhz clock to the sync pin. do not leave this pin foating. the resistor tied from the rt pin to ground should be chosen such that the ltm8031 oscillates 20% lower than the intended synchronization frequency (see the frequency selection section). the ltm8031 will not enter burst mode operation while synchronized to an external clock, but will instead skip pulses to maintain regulation. shorted input protection care needs to be taken in systems where the output will be held high when the input to the ltm8031 is absent. this may occur in battery charging applications or in battery back-up systems where a battery or some other supply is diode ored with the ltm8031s output. if the v in pin is allowed to foat and the run/ss pin is held high (either by a logic signal or because it is tied to v in ), then the ltm8031s internal circuitry will pull its quiescent current through its internal power switch. this is fne if your system can tolerate a few milliamps in this state. if you ground the run/ss pin, the internal switch current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the ltm8031 can pull large currents from the output through the v in pin, potentially damaging the a pplica t ions i n f or m a t ion figure 2. the input diode prevents a shorted input from discharging a back-up battery tied to the output. it also protects the circuit from a reversed input. the ltm8031 runs only when the input is present v out v in run/ss bias r t adj ltm8031 8031 f02 v out gnd v in aux sync device. figure 2 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. pcb layout most of the headaches associated with pcb layout have been alleviated or even eliminated by the high level of integration of the ltm8031. the ltm8031 is neverthe - less a switching power supply and care must be taken to minimize emi and ensure proper operation. even with the high level of integration, you may fail to achieve specifed operation with a haphazard or poor layout. see figure 3 for a suggested layout. ensure that the grounding and heat sinking are acceptable. a few rules to keep in mind are: 1. place the r adj and r t resistors as close as possible to their respective pins. 2. place the c in capacitor as close as possible to the v in and gnd connection of the ltm8031. if a capacitor is connected to the fin terminals, place it as close as possible to the fin terminals, such that its ground connection is as close as possible to that of the c in capacitor. 3. place the c out capacitor as close as possible to the v out and gnd connection of the ltm8031. 8031 f01 i l 0.5a/div v run/ss 2v/div v out 2v/div run/ss gnd 0.22f run 15k 2ms/div figure 1. to soft-start the ltm8031, add a resistor and capacitor to the run/ss pin
ltm8031 13 8031fb a pplica t ions i n f or m a t ion 4. place the c in and c out capacitors such that their ground currents fow directly adjacent or underneath the ltm8031. 5. connect all of the gnd connections to as large a copper pour or plane area as possible on the top layer. avoid breaking the ground connection between the external components and the ltm8031. 6. use vias to connect the gnd copper area to the boards internal ground plane. liberally distribute these gnd vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of ltm8031. however, these capacitors can cause problems if the ltm8031 is plugged into a live or fast rising or falling supply (see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an under-damped tank circuit, and the voltage at the v in pin of the ltm8031 can ring to twice the nominal input voltage, possibly exceed- ing the ltm8031s rating and damaging the part. a similar phenomenon can occur inside the ltm8031 module, at the output of the integrated emi flter, with the same potential of damaging the part. if the input supply is poorly controlled or the user will be plugging the ltm8031 into an energized supply, the input network should be designed to prevent this overshoot. fig - ure 4 shows the waveforms that result when an ltm8031 circuit is connected to a 24v supply through six feet of 24- gauge twisted pair. the frst plot (4a) is the response with a 2.2f ceramic capacitor at the input. the input voltage figure 3. layout showing suggested external components, gnd plane and thermal vias gnd c out c in 8031 f03 v in fin run/ss sync pgood r adj r t aux bias v out gnd optional fin capacitor
ltm8031 14 8031fb a pplica t ions i n f or m a t ion rings as high as 35v and the input current peaks at 20a. one method of damping the tank circuit is to add another capacitor with a series resistor to the circuit, as shown in figure 4b. a 0.7 resistor is added in series with the input to eliminate the voltage overshoot (it also reduces the peak input current). a 0.1f capacitor improves high frequency fltering. for high input voltages its impact on effciency is minor, reducing effciency less than one-half percent for a 5v output at full load operating from 24v. by far the most popular method of controlling overshoot is shown in figure 4c, where an aluminum electrolytic capacitor has been connected to fin. this capacitor s high equivalent series resistance damps the circuit and elimi - nates the voltage overshoot. the extra capacitor improves low frequency ripple fltering and can slightly improve the effciency of the circuit, though it is likely to be the largest component in the circuit. placing the electrolytic capacitor at the fin terminals can also improve the ltm8031s emi fltering as well as guard against overshoots caused by the q of the integrated flter. thermal considerations the ltm8031 output current may need to be derated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power. the amount of current derating is dependent upon the input voltage, output power and ambient temperature. the temperature rise curves given in the typical performance characteristics section can be used as a guide. these curves were generated by a ltm8031 mounted to a 35cm 2 4-layer fr4 printed circuit board. boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended systems line, load and environmental operating conditions. the junction-to-air and junction-to-board thermal resis - tances given in the pin confguration diagram may also be used to estimate the ltm8031 internal temperature. these thermal coeffcients are determined per jesd 51 - 9 (jedec standard, test boards for area array surface mount package thermal measurements) through analysis and physical correlation. bear in mind that the actual thermal resistance of the ltm8031 to the printed circuit board depends upon the design of the circuit board. the die temperature of the ltm8031 must be lower than the maximum rating of 125c, so care should be taken in the layout of the circuit to ensure good heat sinking of the ltm8031. the bulk of the heat fow out of the ltm8031 is through the bottom of the module and the lga pads into the printed circuit board. consequently a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. please refer to the pcb layout section for printed circuit board design suggestions. finally, be aware that at high ambient temperatures the internal schottky diode will have signifcant leakage current increasing the quiescent current of the ltm8031.
ltm8031 15 8031fb typical applica t ions figure 4. a well chosen input network prevents input voltage overshoot and ensures reliable operation when the ltm8031 is hot-plugged to a live supply + ltm8031 4.7f v in 20v/div i in 10a/div 20s/div v in closing switch simulates hot plug i in (4a) (4b) low impedance energized 24v supply stray inductance due to 6 feet (2 meters) of twisted pair + ltm8031 4.7f 0.1f 0.7 v in 20v/div i in 10a/div 20s/div danger ringing v in may exceed absolute maximum rating (4c) + 4.7f 22f 35v ai.ei. 8031 f04 v in 20v/div i in 10a/div 20s/div + v in ltm8031 v in fin
ltm8031 16 8031fb typical applica t ions 0.82v step-down converter 1.8v step-down converter rt share 191k *running voltage range. see applications for start-up details 56.2k v in fin 1f 100f v out 1.8v 1a run/ss v in * 9v to 24v pgood bias ltm8031 aux out sync gnd 8031 ta03 adj rt share 5.11m *running voltage range. see applications for start-up details 69.8k v in fin 1f 200f v out 0.82v 1a run/ss v in * 3.6v to 15v pgood bias ltm8031 aux out sync gnd 8031 ta02 adj
ltm8031 17 8031fb typical applica t ions 2.5v step-down converter 5v step-down converter rt share 115k *running voltage range. see applications for start-up details 61.9k v in fin 1f 47f v out 2.5v 1a run/ss v in * 3.6v to 36v 3.3v pgood bias ltm8031 aux out sync gnd 8031 ta04 adj rt share v in fin 1f 10f 46.4k 29.4k v out 5v 1a run/ss v in * 6.8v to 36v pgood bias ltm8031 aux out sync gnd 8031 ta05 adj *running voltage range. see applications for start-up details 3.3v step-down converter rt share v in fin 1f 22f 78.7k 48.7k v out 3.3v 1a run/ss v in * 4.75v to 36v pgood bias ltm8031 aux out sync gnd 8031 ta08 adj *running voltage range. see applications for start-up details
ltm8031 18 8031fb typical applica t ions package pho t ograph two ltm8031s operating in parallel (also see the ltm8032, 2a pin compatible) rt share v in fin 1f 13.7k 23.7k 8031 ta07 10f v out 8v 1.9a run/ss v in * 11.5v to 36v optional sync tie to gnd if not used pgood bias ltm8031 aux out sync gnd adj rt share 23.7k v in fin 1f run/ss pgood bias ltm8031 aux out sync gnd adj *running voltage range. see applications for start-up details
ltm8031 19 8031fb p ackage descrip t ion lga package 71-lead (15mm 9mm 2.82mm) (reference ltc dwg # 05-08-1823 rev ?) 9.00 bsc package top view lga 71 0108 rev ? 15.00 bsc 4 pad 1 corner 3 pads see notes x y aaa z aaa z 2.670 ? 2.970 detail a package side view detail a substrate mold cap 0.27 ? 0.37 2.40 ? 2.60 bbb z z 1.270 bsc 0.635 0.025 sq. 71x 12.700 bsc 7.620 bsc pad 1 ? (0.635) package in tray loading orientation 2.540 2.540 1.270 5.080 5.080 6.350 6.350 3.810 3.810 0.000 1.270 3.810 3.810 2.540 2.540 1.270 1.270 0.000 suggested pcb layout top view ltmxxxxxx module tray pin 1 bevel component pin 1 package bottom view 67 5 1234 l k j h g f e d c b a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 and spp-020 5. primary datum -z- is seating plane 6. the total number of pads: 71 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature detail a s yxeee detail a symbol aaa bbb eee tolerance 0.15 0.10 0.05 1.27 bsc
ltm8031 20 8031fb p ackage descrip t ion pin signal description a1 v out a2 v out a3 v out a4 v out a5 gnd a6 gnd a7 gnd b1 v out b2 v out b3 v out b4 v out b5 gnd b6 gnd b7 gnd c1 v out c2 v out c3 v out c4 v out c5 gnd c6 gnd c7 gnd d1 v out d2 v out d3 v out d4 v out d5 gnd d6 gnd d7 gnd e1 gnd e2 gnd e3 gnd e4 gnd e5 gnd e6 gnd e7 gnd pin signal description f1 gnd f2 gnd f3 gnd f4 gnd f5 gnd f6 gnd f7 gnd g1 gnd g2 gnd g3 gnd g4 gnd g5 gnd g6 gnd g7 rt h1 gnd h2 gnd h3 gnd h4 bias h5 aux h6 gnd h7 share j5 gnd j6 gnd j7 adj k1 v in k2 v in k3 fin k5 gnd k6 gnd k7 pgood l1 v in l2 v in l3 fin l5 run/ss l6 sync l7 gnd table 3. ltm8031 pinout (sorted by pin number)
ltm8031 21 8031fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/10 addition to features changes to applications information 1 11 b 04/12 added mp-grade part. refected throughout the data sheet 1-22
ltm8031 22 8031fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2009 lt 0412 rev b ? printed in usa r ela t e d p ar t s part number description comments ltm4606 ultralow noise 6a dc/dc module regulator 4.5v v in 28v, 0.6v v out 5v, 15mm w 15mm w 2.8mm lga ltm4612 ultralow noise high v out dc/dc module regulator 5a, 5v v in 36v, 3.3v v out 15v, 15mm w 15mm w 2.8mm lga ltm8023 36v, 2a dc/dc module regulator 3.6v v in 36v, 0.8v v out 10v, 9mm w 11.75mm w 2.8mm lga ltm8025 36v, 3a dc/dc module regulator 3.6v v in 36v, 0.8v v out 24v, 9mm w 15mm w 4.32mm lga ltm8032 36v, 2a emc dc/dc module regulator en55022 class b, 9mm w 15mm w 2.8mm lga. pin compatible with the ltm8031 8v step-down converter rt share v in fin 1f 4.7f 26.7k 23.7k v out 8v 1a run/ss v in * 10.5v to 36v pgood bias ltm8031 aux out sync gnd 8031 ta06 adj *running voltage range. see applications for start-up details typical applica t ion

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